The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A memory device includes a memory device controller and one or more memory integrated circuit chips in communication with the memory device controller. The memory device controller sends commands to the memory integrated circuit chips for execution. For example, the memory device controller may send write commands to store data in the memory integrated circuit chips. One type of memory device is binary and Multi-Level Cell (MLC) NAND flash memory capable of high data storage densities and high performance. In NAND flash, a “page” or group of bits at a time is written to the non-volatile memory.
However, a power failure (such as due to hot removal, brownout, blackout or the like) may cause data corruption or loss when writing data to memory. In flash memory, if a power failure occurs during a write cycle/program operation, something less than all of the bits of the page may be programmed successfully in the non-volatile memory. When the page containing unsuccessfully programmed bits is read back, some bits may have the new value, some will have the old value and, as a result, the page may be corrupted.
Overview
In one aspect, a memory integrated circuit chip is disclosed. The memory integrated circuit chip is configured to communicate with a memory device controller and includes: a command receiving module configured to receive a command from the memory device controller; a command execution module configured to execute the command received; and an indicator module configured to store an address and an associated indicator in the memory integrated circuit chip, the indicator indicative of execution of the command by the memory integrated circuit chip at the address.
In another aspect, a method for a memory integrated circuit chip to communicate with a memory device controller is disclosed. The method is performed by the memory integrated circuit chip and includes: receiving a command from the memory device controller; executing the command at an address within the memory integrated circuit chip; storing in the memory integrated circuit chip the address and one or more indicators, the one or more indicators being stored associated with the address and indicative of execution of the command; and sending the address and the one or more indicators to the memory device controller.
In yet another aspect, a memory device controller is disclosed. The memory device controller includes: a memory integrated circuit chip inquiry module configured to send an inquiry to a memory integrated circuit chip, the inquiry indicative of requesting the memory integrated circuit chip to send one or more flag values and associated addresses, the one or more flag values indicative of execution of a command at the associated addresses by the memory integrated circuit chip; and an abort identification module configured to identify, based on the one or more flag values and associated addresses, a section of memory within the memory integrated circuit chip containing valid data resulting from proper execution of the command or invalid data resulting from aborted execution of the command.
In still another aspect, a method for a memory device controller to communicate with a memory integrated circuit chip in order to determine whether a command abort has occurred is disclosed. The method is performed by the memory device controller and includes: sending a polling command to the memory integrated circuit chip requesting information as to execution of a command by the memory integrated circuit chip; responsive to sending the polling command, receiving address and one or more indicators indicative of the execution of the command by the memory integrated circuit chip; and determining, based on the address and the one or more indicators, a section of memory within the memory integrated circuit chip containing valid data resulting from proper execution of the command or invalid data resulting from aborted execution of the command.
Other features and advantages will become apparent upon review of the following drawings, detailed description and claims. Additionally, other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. The embodiments will now be described with reference to the attached drawings.